1. Field of the Invention
The field of our invention relates generally to semiconductor manufacturing, and more particularly to an apparatus and method for stripping resist from a substrate in a transfer chamber, while at substantially the same time, another substrate is being transferred between a load lock chamber and the transfer chamber of the system. Therefore, throughput is increased because processing and transferring of the substrate occurs in parallel instead of as two separate events.
2. Description of Related Art
During the process of semiconductor fabrication, photoresist, a light sensitive film, is often deposited on a wafer surface and then "exposed" using high intensity light through a mask. The exposed photoresist is then dissolved off the wafer with developers. The pattern of photoresist remaining after development will prevent subsequent etch or implant operations in some areas while allowing etching or implant in other areas. Once the etch or implant operation is completed, the remaining photoresist is removed or stripped from the wafer surface.
A prior art chemical vapor deposition system 100 that can be adapted to remove photoresist from a wafer is illustrated in FIG. 1. The prior art system comprises a load lock chamber 125 and a transfer chamber 105. A complicated robot 130 with one platen 135, a first cassette 140 for holding wafers and a second cassette 150 are disposed within the load lock chamber 125. The transfer chamber 105 includes six fins (110a-110f) mounted to a common center 120 on one end of each fin. The other end of each of the fins (110a-110f) is coupled to a processing stage (115a-115f). There are six processing stages (115a-115f) in the transfer chamber 105.
Under the prior art system 100, the tact time was defined as the sum of the process time (typically about 15 seconds) plus loading time (typically about twenty-seven seconds) for a total of forty-two seconds. The process time is defined as the time that a wafer spends at each stage (e.g., 115a) in the transfer chamber 105 and the loading time is defined as the amount of time spent transferring a new (meaning "unprocessed" by system 100) or processed wafer between the load lock chamber 125 and the transfer chamber 105. Under the prior art system, when a wafer was being processed, a wafer could not be loaded. The converse was also true; when a wafer was being loaded, another wafer could not be processed. Thus, the wafer processing time and the wafer loading time were two separate events in the prior art system 100.
A typical loading sequence would comprise the following actions. For the sake of simplicity, only the movement of one fin is discussed as opposed to the entire fin assembly (which includes all the fins 110a-110f). Fin 110a would move up while the robot 130 would move with its platen 135 toward the fin 110a. The fin 110a would move down and transfer the processed wafer on to the platen 135 of the robot 130. The robot 130 would then retract and rotate toward a first cassette 140 or a second cassette 150. Assuming that the robot rotated toward first cassette 140, the robot 130 would then extend its platen 135 toward first cassette 140. The robot 130 would index and transfer the processed wafer back into the first cassette 140. After doing this, the robot 130 would retract and then index forward to the next wafer slot on the first cassette 140. The robot 130 would extend its platen 135 toward the first cassette 140. The robot 130 would index so that a new wafer is transferred onto the robot's platen 135. The robot 130 would then retract and rotate toward fin 110a. The robot 130 would then extend the platen 135 toward the fin 110A. The fin 110a (including the fin assembly) would move up to receive the new wafer. The robot 130 would retract after the wafer was transferred to the fin 110a. The fin 110a would then rotate towards processing stage 115b and then move down so that fin 110a is now located where fin 110b was located. In other words, all six fins (110a-110f) have moved in a counterclockwise direction since all six fins (110a-110f) are attached to a common center 120. Thus, fin 110a will then move down so that the wafer is now on processing stage 115b. The entire sequence of events typically takes about 27 seconds to unload a processed wafer from the transfer chamber to the load lock chamber and then back into a cassette (140 or 150) and to load a new wafer into the transfer chamber. During this transfer sequence, all processing stops.
Once a new wafer is introduced into the transfer chamber 105, processing of the wafer resumes. The processing time usually takes about 15 seconds. While a wafer is being processed in the transfer chamber 105, the robot 130 is inactive and no wafers are being loaded or unloaded between the load lock chamber 125 and the transfer chamber 105.
When a second wafer is introduced into the transfer chamber 105, the first wafer which was on processing stage 115b will be moved to processing stage 115c so that the new wafer may be placed on processing stage 115b. However, during the loading and unloading sequence, the processing of the wafers inside the transfer chamber 105 must cease. Thus, throughput is greatly reduced because the wafers cannot be processed in parallel with the wafers being loaded and unloaded between the load lock chamber 125 and the transfer chamber 105.
It was a common belief that if one sacrificed one of the process stages in the transfer chamber to act solely as a loading and unloading station, then a loss in throughput would occur. Therefore, all the previous solutions continued to utilize all six wafer stages as processing stages and to separate the processing of wafers from the transferring of wafers into two events. It was also believed that if one introduced a complicated mechanism inside a process environment, it would create a contamination problem for the wafers. Thus, most of the complicated robotic mechanisms used were in the load lock chamber and not in the transfer chamber where the processing occurred.
Thus, what is needed is a wafer transfer mechanism inside the transfer chamber that will allow the wafer loading time to substantially parallel the wafer processing time in order to increase throughput at a reduced cost and without introducing contamination concerns into the process environment.